1. Field of the Invention
The present invention relates to a semiconductor memory device such as an SRAM.
2. Description of the Related Art
Recently, technologies for lowering operating voltages and achieving high speed operation in the SRAM have been developed progressively and various prior art technologies have been proposed to improve the cell disturb characteristic. One is associated with an SRAM having a hierarchical bit-line structure with less memory cells per bit line to reduce the bit-line capacity (Non-patent Document 1: John Wuu et. al., 2005 IEEE International Solid-State Circuits Conference, pp. 488-489, 618). Data reading in the SRAM is executed as follows. A precharge circuit is used to precharge a pair of bit lines to “H” level and one of the paired bit lines is connected to a cell node at “L” level in a selected memory cell, thereby lowering the one bit line from “H” level to “L” level. This operation is transferred to the sense node through a column gate and amplified at a sense circuit connected to the sense node and provided to external. Thus, data reading can be achieved.
In the above operation, however, when the voltage on the bit line lowers by the threshold than the gate voltage on the column gate, the column gate turns on. Thus, the bit line is connected to the sense node and influenced by the capacity on the sense node. In accordance with this influence, the rate of lowering the voltage on the bit line is decreased. In this case, the bit line voltage on the selected memory cell does not lower sufficiently and causes deterioration of the disturb characteristic of the memory cell.